An efficient OFDM carrier system design using parallel architecture

The objective of this design is to made a design of 128/64 point Fast Fourier transform processor to support future generation MultipleInput Multiple Output Orthogonal Frequency Division Multiplexing (MIMO -OFDM). 1n wireless local area network base band processor the architecture produces high complexity. The pipelined mixed radix multipath delay feedback (MRMDF) FFT architecture is proposed to provide as higher throughput rate combining the characteristics of both Single path Delay Feedback (SDF) which is used to reduce memory size . The proposed processor not only supports the operation of FFT in 128 point and 64 point but can also provide different throughput rates .And also less hardware complexity is needed in this deign compared with conventional four. This approach will also reduce the power consumption. The proposed FFT Processor is designed and implemented in VHDL and the simulation results are presented. This paper discusses the effect of carrier frequency offset and its